The present invention relates to a digital to analogue converting circuit, and in particular to a multi-channel digital to analogue converting circuit for converting digital codes to analogue signals, and also to a single channel digital to analogue converting circuit.
In multi-channel digital to analogue circuits for converting digital codes to analogue signals, in general, each channel of the circuit is provided with a digital to analogue converter (DAC). Such DACs typically comprise a plurality of impedance elements, which may be, for example, resistors or capacitors. In resistor DACs the transistors may, for example, be arranged in an R-2R ladder, a string or other suitable formation. In capacitor DACs the capacitor may, for example, be arranged in a binary weighted array or any other suitable arrangement. In order to ensure accuracy of each DAC, it is essential that the impedance elements within each DAC are accurately matched to each other, otherwise, the integral linearity of the DAC will be poor. Matching of such impedance elements in a DAC when implemented in integrated circuit chips is relatively difficult, and is also relatively expensive. In general, in order to adequately match the impedance elements a relatively large chip area is required for forming each DAC, which leads to significant expense and inefficiency. An alternative approach in the provision of relatively high accuracy DACs is to form the impedance elements of the respective DACs to be suitable for laser or fuse trimming. However, this also adds to the expense of producing such DACs. A further alternative approach is to provide on-chip calibration circuitry for storing algorithms to correct for mismatched impedance elements in the respective DACs. However, the provision of such on-chip calibration circuitry requires additional chip area, and thus adds to the expense of producing such DACs.
It is, however, known to provide a multi-channel digital to analogue circuit in which a single DAC is provided for converting a digital input code to an analogue signal, which is in turn sampled onto one or more of the channels of the multi-channel circuit. Each channel comprises a sample and hold circuit which samples and holds the analogue signal on an analogue output of the sample and hold circuit. While such multi-channel digital to analogue circuits avoid the need to provide a DAC for each channel, they suffer from a serious disadvantage in that typically the sample and hold circuits are capacitive circuits, and thus the analogue signal which is being held on the analogue output of each channel decays relatively rapidly. This requires periodic sampling of the output of the DAC in order to return the decaying analogue signal to its correct value. Relatively complex additional circuitry is required to carry out the periodic sampling of the DAC output. A further disadvantage of such a multi-channel circuit is that the analogue signal must be held on the DAC output to permit periodic sampling, thereby limiting the data throughput of such multi-channel circuits.
There is therefore a need for a multi-channel DAC which permits outputting of relatively accurate outputs on the respective channels, while at the same time minimising the number of accurate DACs required.
According to the invention there is provided a multi-channel digital to analogue circuit for converting digital codes to analogue signals, the circuit comprising:
a primary digital to analogue converter (DAC) for receiving digital input codes and outputting corresponding analogue signals,
a plurality of infinite sample and hold circuits for sampling the analogue signals outputted by the primary DAC and for holding an analogue signal similar to that sampled from the primary DAC, the infinite sample and hold circuits defining respective analogue outputs of the multi-channel circuit, and
a primary switching mechanism for selectively sampling analogue signals outputted by the primary DAC onto the infinite sample and hold circuits.
In one embodiment of the invention the primary switching mechanism sequentially samples the analogue signals outputted by the primary DAC onto respective selected ones of the infinite sample and hold circuits. Alternatively, the primary switching mechanism simultaneously samples the analogue signal outputted by the primary DAC onto respective selected ones of the infinite sample and hold circuits.
In another embodiment of the invention the primary switching mechanism comprises a plurality of primary switches, one primary switch being provided for each infinite sample and hold circuit for selectively sampling the analogue signal outputted by the primary DAC onto the corresponding infinite sample and hold circuit.
In a further embodiment of the invention a primary control circuit is provided for selectively addressing the primary switches of the primary switching mechanism.
In one embodiment of the invention each infinite sample and hold circuit comprises a secondary DAC having an analogue output from which the analogue signal held on the analogue output of the infinite sample and hold circuit is derived, and an analogue to digital converting circuit for deriving from each analogue signal sampled by the infinite sample and hold circuit a digital code which corresponds to an analogue signal from the secondary DAC which is similar to the sampled analogue signal, and for applying the derived digital code to the secondary DAC.
Preferably, the digital code derived by the analogue to digital converting circuit of each infinite sample and hold circuit is stored in the analogue to digital converting circuit until the next analogue signal is sampled by the infinite sample and hold circuit.
Preferably, each infinite sample and hold circuit is configurable to operate in an acquisition mode during which the digital code for the secondary DAC is derived, and in a hold mode during which the analogue signal outputted by the secondary DAC is held on the analogue output of the infinite sample and hold circuit.
In another embodiment of the invention the analogue to digital converting circuit of each infinite sample and hold circuit comprises a successive approximation register for deriving the digital code for the secondary DAC when the infinite sample and hold circuit is configured in the acquisition mode, and for latching the derived digital code onto the digital input of the secondary DAC when the infinite sample and hold circuit is configured in the hold mode.
In another embodiment of the invention a secondary switching mechanism is provided in each infinite sample and hold circuit for configuring the infinite sample and hold circuit to operate in the respective acquisition and hold modes, the secondary switching mechanism being responsive to the successive approximation register having derived the digital code for the secondary DAC for switching the infinite sample and hold circuit from the acquisition mode to the hold mode, and being responsive to the primary switching mechanism sampling the next analogue signal from the primary DAC to the infinite sample and hold circuit for switching the infinite sample and hold circuit from the hold mode to the acquisition mode.
In one embodiment of the invention each infinite sample and hold circuit comprises an amplifier which is configurable as a buffer when the infinite sample and hold circuit is configured in the hold mode for applying the output from the secondary DAC to the analogue output of the infinite sample and hold circuit, and the amplifier is configurable as a comparator when the infinite sample and hold circuit is configured in the acquisition mode for sequentially comparing the outputs of the secondary DAC with the sampled analogue signal from the primary DAC and for outputting corresponding signals to the successive approximation register for driving the successive approximation register to derive digital code for the secondary DAC.
In another embodiment of the invention a primary input is provided to the primary DAC for inputting a primary digital input code to the primary DAC, and at least one of the infinite sample and hold circuits is provided with a secondary input for inputting a secondary digital input code to the secondary DAC of the infinite sample and hold circuit for facilitating altering of the analogue signal on the analogue output of the infinite sample and hold circuit when the infinite sample and hold circuit is configured in the hold mode.
Preferably, each infinite sample and hold circuit is provided with a secondary input to the corresponding secondary DAC.
Advantageously, each secondary DAC is of higher resolution than the primary DAC.
In one embodiment of the invention the differential linearity of each secondary DAC is better than the differential linearity of the primary DAC.
In another embodiment of the invention the integral linearity of the primary DAC is better than the integral linearity of each secondary DAC.
Additionally, the invention provides a digital to analogue converting circuit comprising:
a primary DAC having a primary input thereto for receiving a primary digital input code to the primary DAC,
an infinite sample and hold circuit for sampling the analogue signals outputted by the primary DAC and for holding an analogue signal similar to that sampled from the primary DAC on an analogue output of the infinite sample and hold circuit, the infinite sample and hold circuit comprising
a secondary DAC having an analogue output from which the analogue signal held on the analogue output of the infinite sample and hold circuit is derived,
an analogue to digital converting circuit for deriving from each analogue signal sampled by the infinite sample and hold circuit a digital code which corresponds to an analogue signal from the secondary DAC which is similar to the sampled analogue signal, and for applying the derived digital code to the secondary DAC,
the infinite sample and hold circuit being configurable in an acquisition mode for deriving the digital code for the secondary DAC, and in a hold mode in which the analogue signal outputted by the secondary DAC is held on the analogue output of the infinite sample and hold circuit, and
a secondary input being provided to the secondary DAC for inputting a secondary digital input code to the secondary DAC for altering the analogue signal on the analogue output of the infinite sample and hold circuit when the infinite sample and hold circuit is operating in the hold mode.
In one embodiment of the invention the secondary DAC is of higher resolution than the primary DAC for increasing the overall resolution of the digital to analogue circuit.
In another embodiment of the invention the differential linearity of the secondary DAC is better than the differential linearity of the primary DAC.
In a further embodiment of the invention the integral linearity of the primary DAC is better than the integral linearity of the secondary DAC.
The advantages of the invention are many. The multi-channel digital to analogue converting circuit according to the invention can be provided at relatively low cost with minimum area of an integrated circuit chip being required. By virtue of the fact that each infinite sample and hold circuit can independently and in theory, in time, infinitely hold an analogue signal on the corresponding analogue output terminal of the selected channel of the multi-channel circuit which is similar to the analogue output of the primary DAC, once the primary DAC is an accurate DAC having a relatively high integral linearity performance, the integral linearity performance of the secondary DACs is relatively unimportant. However, it is desirable that the secondary DACs should have a relatively high resolution, in other words, a relatively high differential linearity performance, in order that the analogue signal held on the analogue output relatively closely approximates to the sampled analogue signal. Accordingly, since it is only necessary for the primary DAC to have a relatively high integral linearity performance, it is only necessary to have the impedance elements, be they resistors, capacitors or otherwise, accurately matched in the primary DAC. Matching of the impedance elements in the secondary DACs is relatively unimportant. Accordingly, it is possible according to the invention to provide a multi-channel digital to analogue converting circuit wherein only one of the DACs, namely, the primary DAC need be an accurate DAC having a relatively high integral linearity performance.
By providing a secondary digital input for inputting secondary digital input codes to the secondary DACs of the respective infinite sample and hold circuits of the respective channels, it is possible by providing the secondary DACs with resolutions higher than the primary DAC to provide a multi-channel digital to analogue converting circuit with a resolution higher than the resolution of the primary DAC, the resolution of the multi-channel circuit being a function of the resolution of the respective secondary DACs.
When the circuit is provided as a single channel digital to analogue converting circuit it is possible to boost the resolution of the primary DAC by providing a secondary DAC with a higher resolution than the primary DAC, and the advantage of this is that once the primary DAC is of good integral linearity performance the integral linearity performance of the secondary DAC is relatively unimportant, all that is required of the secondary DAC is that it is of high resolution and of good differential linearity performance.
The invention will be more clearly understood from the following description of an embodiment thereof, which is given by way of example only, with reference to the accompanying drawings.